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cym9270 cym9271b cym9272a cym9273 64k x 36 sram module 128k x 36 sram module 256k x 36 sram module 512k x 36 sram module cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05135 rev. ** revised march 27, 2002 72a features operates at 50 mhz uses 64k x 18 / 128k x 18 or 256k x 18 high-performance synchronous srams 144-position angled dimm from berg p/n 61178 3.3v inputs/data outputs functional description the cym9270, cym9271b, cym9272a, and the cym9273 are high-performance synchronous memory modules orga- nized as 64k(9270), 128k(9271b), 256k(9272a), 512k(9273) by 36 bits. these modules are constructed using either 128k x 18 srams (9270, 9271b, 9272a) or 256k x 18 srams (9273) in plastic surface mount packages on an epoxy lami- nate board with pins. the modules are designed to be incor- porated into large memory arrays. the modules are configured as single banks or multiple banks depending on the sram used to make the module. separate clock are provided for each of the banks. separate clocks are provided for each of the srams. multiple ground pins and on-board decoupling capacitors en- sure high performance with maximum noise immunity. all components on the cache modules are surface mounted on a multi-layer epoxy laminate (fr-4) substrate. the contact pins are plated with 150 micro-inches of nickel covered by 30 micro-inches of gold flash. logic block diagram - cym9270 d[0:31] dq[0:3] a[15:0] cs bw[0:3] pd 1 pd 0 gnd nc d[0:15] dq[0:1] clk oe we 64kx36 (2) 128k x 18 srams clk[0:1] weh wel adsc a 15:0 sgw oe cs clk[0:1] bwe bank 0 bank0 adsp cs oe
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 2 of 11 logic block diagram- cym9271b/cym9272a d[0:31] dq[0:3] a[16:0] cs[0:1] bw[0:3] pd 1 pd 0 nc gnd d[0:15] dq[0:1] clk adsc a 16:0 sgw oe cs d[0:15] dq[0:1] clk oe[0:1] we 128kx36 256kx36 gnd gnd (2) 128k x 18 srams (2) 128k x 18 srams clk[0:1] clk[2:3] weh wel adsc a 16:0 sgw oe cs weh wel clk[0:3] bwe bwe bank0 bank1 bank0 bank0 and bank1 adsp cs1 cs0 oe1 oe0
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 3 of 11 logic block diagram- cym9273 d[0:31] dq[0:3] a[17:0] cs[0:1] bw[0:3] pd 1 pd 0 d[0:15] dq[0:1] clk oe[0:1] we (2) 256k x 18 srams clk[0:1] weh wel adsc a 17:0 sgw oe cs clk[0:3] bwe bank1 d[0:15] dq[0:1] clk (2) 256k x 18 srams weh wel adsc a 17:0 sgw oe cs bwe adsp bank0 clk[2:3] 512kx36 bank0 and 1 nc nc cs[0] cs[1] oe1 oe0
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 4 of 11 pin configuration top view dual read-out simm (dimm) 10 9 56 7 8 4 1 2 gnd gnd v cc3 3 90 89 85 86 87 88 84 81 82 83 20 19 15 16 17 18 14 11 12 13 30 29 25 26 27 28 24 21 22 d 30 d 28 d 24 d 22 d 26 23 39 35 36 37 38 34 31 32 d 20 d 14 d 12 dq 1 d 18 33 40 41 42 52 51 47 48 49 50 46 43 44 d 8 d 6 d 4 d 0 a 3 d 2 45 57 58 59 60 56 53 54 a 5 gnd a 2 55 69 65 66 67 68 64 61 62 gnd 63 70 79 75 76 77 78 74 71 72 73 80 gnd d 21 100 99 95 96 97 98 94 91 92 93 d 29 d 23 d 27 d 25 110 109 105 106 107 108 104 101 102 103 d 19 d 17 d 15 d 13 120 119 115 116 117 118 114 111 112 113 d 11 121 122 d 9 d 7 d 5 d 3 d 1 127 128 129 130 126 123 124 125 gnd a 6 140 139 135 136 137 138 134 131 132 133 pd 0 a 4 144 141 142 143 a 9 a 16 a 12 a 13 d 16 gnd cs[0] a 8 a 10 a 14 a 15 pd 1 v cc3 v cc3 a 1 a 0 a 7 a 11 v cc3 gnd clk0 clk1 v cc3 d 10 clk3 clk2 v cc3 gnd gnd d 31 gnd gnd dq 0 dq 2 dq 3 gnd gnd a 17 nc nc gnd bw[2] cs[1] oe[1] adsp nc nc nc v cc3 v cc3 v cc3 bw[3] we gnd gnd gnd nc nc nc gnd gnd gnd gnd gnd v cc3 v cc3 v cc3 v cc3 oe[0] bw[0] gnd bw[1] gnd v cc3 nc nc nc nc nc nc nc nc nc nc nc nc gnd gnd v cc3 nc gnd nc nc nc nc v cc3 nc nc nc nc nc
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 5 of 11 pin definitions signal description v cc3 3v supply gnd ground a[17:0] addresses from processor adsp address strobe from the processor oe[1:0] output enables for each of the banks bw[0:3] byte writes we global write cs [1:0] chip select for the two banks pd 0 ? pd 1 presence detect output pins d[31:0] data lines from processor dq[3:0] data parity lines from processor clk[0:3] clock lines to the module. nc signal not connected on module rsvd reserved presence detect pins pd 1 pd 0 cym9270 ? 64k x 36 gnd nc cym9271b ? 128k x 36 nc gnd cym9272a ? 256k x 36 gnd gnd cym9273 ? 512k x 36 nc nc
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 6 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +125 c ambient temperature with power applied ........................................ ? 0 c to +70 c 3.3v supply voltage to ground potential ..... ? 0.5v to +4.5v dc voltage applied to outputs in high z state .............................................. ? 0.5v to +4.6v dc input voltage ........................................... ? 0.5v to +4.6v output current into outputs (low)............................. 20 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 5% electrical characteristics over the operating range parameter description test condition min. max. unit v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v v oh output high voltage v cc = min., i oh = ? 4 ma 2.4 v v ol output low voltage v cc = min., i ol = 8 ma 0.4 v i cc (9270) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 350 ma i cc (9271b) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 500 ma i cc (9272a) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 1000 ma i cc (9273) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 1200 ma capacitance [1] parameter description test conditions max. unit c a address input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9270 12 pf 9271b 7 9272a 14 9273 20 c i control input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9270 12 9271b 8 9272a 16 9273 20 c o input / output capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9270 9 9271b 5 9272a 10 9273 16 c clk clock capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9270 6 9271b 3 9272a 3 9273 5 note: 1. tested initially and after any design or process changes that may affect these parameters.
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 7 of 11 ac test loads and waveforms [3] 3.3v gnd 90% 10% 90% 10% 3ns 3 ns output r1 r2 5pf including jigand scope (a) (b) all input pulses output r l = 50 ? v l = 1.5v v ccq [2] switching characteristics over the operating range parameter description cym9270 cym9271b cym9272a cym9273 min. max. min. max. min. max. min. max. unit t cyc clock cycle time 12 12 12 12 ns t ch clock high 4444ns t cl clock low 4444ns t as address set-up before clk rise3333ns t ah address hold after clk rise 0.5 0.5 0.5 0.5 ns t cdv data output valid after clk rise 10.3 10.3 10.3 10.3 ns t doh data output hold after clk rise3333ns t wes wh , wl set-up before clk rise 3.1 3.1 3.1 3.1 ns t weh wh , wl hold after clk rise 0.5 0.5 0.5 0.5 ns t ds data input set-up before clk rise 3.3 3.3 3.3 3.3 ns t dh data input hold after clk rise 0.5 0.5 0.5 ns t css chip select set-up 3.1 3.1 3.1 3.1 ns t csh chip select hold after clk rise 0.5 0.5 0.5 0.5 ns t eoz [4] oe high to output high z 7777ns t eov oe low to output valid 7777ns notes: 2. resistor values for v ccq = 3.3v are r1 = 317 ? and r2 = 351 ? . 3. unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and load capacitance. shown in (a) and (b) of ac test loads. all measurements are at room temperature. 4. t eoz is specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage.
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 8 of 11 switching waveforms single read [5] single write timing notes: 5. oe is low throughout this operation. 6. adsp has no effect on adv , wl , and wh if cs is high. t cl t as t ah t ads t adsh t ch t css t csh t wes t weh t cdv t doh t cyc clk address adsp wh ,wl data out cs [6] t cl t as t ah t ads t adsh t ch t css t csh t wes t weh t ds t dh t eoz clk address adsp wh , wl data in data out oe cs
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 9 of 11 output (controlled by oe ) output timing (controlled by cs ) output timing (controlled by wh / wl ) switching waveforms (continued) t eov oe data out t eoz t css t csh t css t csh t cdv t csoz clk cs data out t ads t adsh t ads t adsh adsp t ads t ads clk t weoz t weov wh , wl data out t wes t weh t adsh t adsh adsp ordering information speed (mhz) ordering code package name package type description operating range 50 cym9270pm-50c pm45 144-pin dual-readout simm sync 64k x 36 commercial cym9271bpm-50c pm45 144-pin dual-readout simm sync 128k x 36 cym9272apm-50c pm46 144-pin dual-readout simm sync 256k x 36 CYM9273PM-50C pm46 144-pin dual-readout simm sync 512k x 36
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 10 of 11 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams 144-pin single-sided dimm pm45 144-pin dual-sided dimm pm46
cym9270 cym9271b cym9272a cym9273 document #: 38-05135 rev. ** page 11 of 11 document title: cym9270, cym9271b, cym9272a, cym9273 64k/128k/256k/512k x 36 sram module document number: 38-05135 rev. ecn no. issue date orig. of change description of change ** 114557 3/28/02 dsg change from spec number: 38-m-00083 to 38-05135

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